A DRAM is subject to erroneous operation during information storage and retrieval, if the noise level exceeds the level of the information signals.
Noise is usually caused by a transient voltage variation produced during start-up the DRAM, a voltage variation due to alpha-particle radiation produced from the chip package penetrating into the semiconductor material, the voltage variations on the bit lines affected by information stored in a selected memory cell of the memory cell array, that is induced by the parasitic capacitance between the word and bit lines.
The structures of conventional DRAMS, that are considerably affected by such noise are illustrated in FIGS. 1 and 2, which respectively show an open-bit-line and folded-bit-line cell array.
Referring to FIG. 1, a reference memory cell consists of a transistor Q and a capacitor Cs, indicated as MC0, MC1, DM0, DM1, and so on. Namely, the conventional DRAM shown in FIG. 1 is formed by arranging a plurality of reference memory cells, wherein the drain of the MOS transistor Q is connected to the bit line, the gate to the word line, and the source to one end of the capacitor Cs. The other end of the capacitor Cs is provided with a reference voltage Vref. CBW represents the parasitic capacitance between the bit and word lines, and 10 is a sense amplifier.
Such reference memory cells are arranged in the opposite directions of the sense amplifier 10, e.g., differential amplifier, which amplifies the voltage difference between the two bit lines BL0 and BL0. In operation of this circuit, the charge stored in the capacitor Cs of a selected reference memory cell representing a "0" or "1" bit is retrieved by switching off the transistor by means of a pulse provided through the word line W0, W1, . . . and precharging the bit line BL, BL, . . . with the reference voltage. In this case, if the word line W1 is chosen, data stored in the capacitors of all the reference memory cells MC1 . . . connected to the word line are transferred through each of the bit lines to the sense amplifier. The sense amplifier senses the slight voltage variation of the bit lines caused by the bit values applied to each of the bit lines, since the bit lines are precharged with the reference voltage. Namely, the sense amplifier amplifies the difference between the selected bit line BL0, BL1, . . . precharged and the unselected bit line BL0, BL0, . . . precharged.
Thus, when there occurs a voltage variation in each of the bit lines, the parasitic capacitance CBW between the bit lines causes a variation in the voltage of the unselected word line, so that noise is introduced into the selected bit line, so as to cause the DRAM to operate erroneously. In this case, the magnitude of the noise increases with an increase in the parasitic capacitance CBW. A typical example of such a conventional DRAM is disclosed in the U.S. Pat. No. 4,044,340.
In order to decrease the cell array noise inherently produced in an open-bit-line type DRAM, a folded-bit-line type DRAM has been proposed. However, it does not sufficiently eliminate noise. Referring to the folded-bit-line type DRAM illustrated in FIG. 2, there a pair of adjacent bit lines BL0, BL0 are arranged in parallel. The bit lines BL and BL are alternately connected with the reference memory cells MC0, MC1 . . . with reference to each word line orthogonal to the bit lines. The operation is performed in the same manner as in FIG. 1. The reference memory cell consists of a transistor Q and capacitor Cs. In the reference memory cell connected to the bit line, the parasitic capacitance between the bit and word lines is indicated by CBW, while the parasitic capacitance at a cross-over-region crossing area of the bit and word lines not having the reference memory cell is indicated by CBWN.
However, this DRAM suffers from cell array noise corresponding to the difference between the parasitic capacitances CBW and CBWN in the bit lines BL0, BL0 connected to the two input terminals of the sense amplifier 10, when there is a voltage variation in each of the bit lines. Such conventional DRAMS are disclosed in the U.S. Pat. Nos. 3,876,992, 3,979,734 and 4,190,466.
In brief, the conventional open-bit-line type DRAM suffers from cell array noise, so that it operates erroneously, because the reference memory cells are formed at crossed-over-regions of the bit and word lines in opposite directions of the sense amplifier. For example, when information bit stored in the capacitor of the memory cell connected to the lowest bit line in one word line of the cell array is a "0", and information bits of all the other capacitors are "1" bits, the data of the lowest bit line, corresponding to a "0" information bits, tends to erroneously increase towards "1".
In addition although the conventional folded-bit-line type DRAM suffers lower cell array noise than the open-bit-line DRAM because of a pair of bit lines being connected in parallel in one side of the sense amplifier, it erroneously operates in the case of the noise of the transient voltage variation and/or the noise of the alpha-particles occurring simultaneously, because the bit lines are alternately connected to one of the memory cells with reference to the word lines.